In optical communication systems, WDM (Wavelength Division Multiplexing) technology is employed to increase bandwidth. Client nodes such as routers use wideband optical signals. An optical wavelength conversion board referred to as a transponder is used to convert the optical signals from client nodes into narrowband optical signals having predetermined wavelengths with a narrow spectrum, and also to convert narrowband optical signals having predetermined wavelengths in the multiplexed domain into wideband optical signals.
FIG. 1 is a drawing showing an example of arrangement of transponders in an optical communication system.
On the left-hand side in FIG. 1, client nodes N11, N12, and so on are connected to respective transponders T11, T12, and so on, which are then connected to a optical wavelength division multiplexing/demultiplexing unit MD1. By the same token, on the right-hand side in FIG. 1, client nodes N21, N22, and so on are connected to respective transponders T21, T22, and so on, which are then connected to a optical wavelength division multiplexing/demultiplexing unit MD2. In a WDM transmission section between the optical wavelength division multiplexing/demultiplexing unit MD1 and the optical wavelength division multiplexing/demultiplexing unit MD2, long-distance transmission is performed by using optical amplifiers A11 and A12 provided along a path extending in one direction and optical amplifiers A21 and A22 provided along a path extending in the opposite direction.
FIG. 2 is a drawing showing an internal configuration of a transponder T (i.e., T11, T12, T21, T22, and so on). It should be noted that a signal direction extending from a client side to a network side (i.e., the side on which an optical wavelength division multiplexing/demultiplexing unit is provided) is hereinafter referred to as an upstream direction, and that a signal direction extending from a network side to a client side is hereinafter referred to as a downstream direction.
In FIG. 2, the transponder T includes an optical transceiver unit 110 for exchanging wideband optical signals with the client side and performing conversion between optical signals and electrical signals, an optical transceiver unit 120 for exchanging narrowband optical signals with the network side and performing conversion between optical signals and electrical signals, and an electrical signal processing unit 130 situated between the optical transceiver units 110 and 120 to perform frame processing, error correction processing, and so on. The error correction processing is performed in the electrical signal processing unit 130 for the purpose of preventing the degradation of error rate that may occur due to waveform deformation through long-distance transmission and the lowering of OSNR (optical signal noise ratio) in optical amplifiers. To this end, error correction codes are attached to signals transmitted to the network side, and FEC (Forward Error Correction) is performed based on the error correction codes received from the network side. Accordingly, the bit rate of signals on the network side is slightly greater than the bit rate of signals on the client side because of the addition of error correction codes.
The transponder T further includes a transmission PLL (Phase-Locked Loop) unit 140 for generating a clock for the network side based on a clock of the signals arriving from the client side, such that that the generated clock has a predetermined frequency ratio, and is synchronized with the base clock. The transponder T further includes a transmission PLL unit 150 for generating a clock for the client side based on a clock of the signals arriving from the network side, such that that the generated clock has frequency in a predetermined proportion to frequency of the base clock, and is synchronized with the base clock.
In the case of normal operation, the optical transceiver unit 120 outputs normal signals in the upstream direction based on the signals from the client side. Similarly, in the case of normal operation, the optical transceiver unit 110 outputs normal signals in the downstream direction based on the signals from the network side.
When a failure such as fiber disconnection occurs in an optical channel, the electrical signal processing unit 130 is required to transmit AIS (Alarm Indication Signal) indicative of the occurrence of failure in a predetermined format in the transmission direction if the product is directed to customers in North America. Namely, upon the occurrence of optical input interruption on the client side, the optical transceiver unit 120 needs to transmit the AIS signals in the upstream direction under the control of the electrical signal processing unit 130. Upon the occurrence of optical input interruption on the network side, on the other hand, the optical transceiver unit 110 needs to transmit the AIS signals in the downstream direction under the control of the electrical signal processing unit 130.
However, the transmission PLL unit 140 generates a network-side clock used by the optical transceiver unit 120 based on a clock of the signals arriving from the client side, and the transmission PLL unit 150 generates a client-side clock used by the optical transceiver unit 110 based on a clock of the signals arriving from the network side. When an optical input interruption occurs in either case, thus, the clock cannot be generated properly. In consideration of this, the clock source needs to be switched over upon detecting an optical input interruption.
FIG. 3 is a drawing showing an internal configuration of a transponder T provided with a clock switching function for use at the time of optical input interruption.
In FIG. 3, with respect to the upstream side (i.e., the side on which signals in the upstream direction are processed), the transponder T further includes, in addition to the configuration shown in FIG. 2, a switchover clock oscillating unit 161 for generating a switchover clock, a clock switchover control unit 162 for generating a clock switchover control signal upon receiving an optical input interruption detection signal from the optical transceiver unit 110, a selector 163 for selecting either the clock from the electrical signal processing unit 130 or the clock from the switchover clock oscillating unit 161 in response to the clock switchover control signal from the clock switchover control unit 162 (i.e., selecting the clock from the electrical signal processing unit 130 during normal operation and the clock from the switchover clock oscillating unit 161 at the time of optical input interruption), and a frequency dividing unit 164 for dividing the frequency of the output of the selector 163 to provide a clock to the transmission PLL unit 140.
With respect to the downstream side (i.e., the side on which signals in the downstream direction are processed), the transponder T further includes a clock switchover control unit 172 for generating a clock switchover control signal upon receiving an optical input interruption detection signal from the optical transceiver unit 120, and also includes a selector 173 for selecting either the clock from the electrical signal processing unit 130 or the clock from the switchover clock oscillating unit 161 in response to the clock switchover control signal from the clock switchover control unit 172 (i.e., selecting the clock from the electrical signal processing unit 130 during normal operation and selecting the clock from the switchover clock oscillating unit 161 at the time of optical input interruption) to provide a clock to the transmission PLL unit 150.
The frequency dividing unit 164 is provided to receive the output of the selector 163 with respect to the upstream side. This is because the switchover clock oscillating unit 161 is set to frequency that matches the bit rate on the client side. It thus suffices for the selector 163 to switch clocks having high frequency for subsequent frequency division. The reason why the switchover clock oscillating unit 161 is set to the frequency that matches the bit rate on the client side is that the client side uses frames such as those of SDH (Synchronous Digital Hierarchy). Because of the use of such frames, a widely available oscillator can be used as the switchover clock oscillating unit 161, which provides cost advantage.
FIG. 4 is a drawing showing the detail of an internal configuration of a clock system used in the transponder T. The same elements as those of FIG. 3 are referred to by the same numerals.
In FIG. 4, the clock switchover control unit 162 for the upstream side receives an optical input interruption detection signal from an optical input interruption detecting unit 111 of the optical transceiver unit 110. By the same token, the clock switchover control unit 172 for the downstream side receives an optical input interruption detection signal from an optical input interruption detecting unit 121 of the optical transceiver unit 120.
The transmission PLL unit 140 for the upstream side (see FIG. 3) includes a frequency dividing unit 141, a flip-flop 142, an EX-NOR gate 143, a low-pass filter 144, a voltage controlled oscillator 145, and a divider 146. The flip-flop 142 and the EX-NOR gate 143 together constitute a phase comparator. By the same token, the transmission PLL unit 150 for the downstream side (see FIG. 3) includes a frequency dividing unit 151, a flip-flop 152, an EX-NOR gate 153, a low-pass filter 154, a voltage controlled oscillator 155, and a divider 156. The flip-flop 152 and the EX-NOR gate 153 together constitute a phase comparator.
In FIG. 3 and FIG. 4, the selector 163 selects the clock from the electrical signal processing unit 130 with respect to the upstream side during the normal operation. The clock arriving from the client side is thus supplied to the transmission PLL unit 140 via the frequency dividing unit 164, so that the network-side clock is generated base on this supplied clock to transmit normal signals from the optical transceiver unit 120 to the network side. By the same token, the selector 173 selects the clock from the electrical signal processing unit 130 with respect to the downstream side during the normal operation. The clock arriving from the network side is thus supplied to the transmission PLL unit 150, so that the client-side clock is generated base on this supplied clock to transmit normal signals from the optical transceiver unit 110 to the client side.
At the time of optical input interruption on the client side, the selector 163 selects the clock from the switchover clock oscillating unit 161 with respect to the upstream side. The clock of the switchover clock oscillating unit 161 is thus supplied to the transmission PLL unit 140 via the frequency dividing unit 164, so that the network-side clock is generated base on this supplied clock to transmit the AIS signals generated by the electrical signal processing unit 130 to the network-side via the optical transceiver unit 120. By the same token, at the time of optical input interruption on the network side, the selector 173 selects the clock from the switchover clock oscillating unit 161 with respect to the downstream side. The clock of the switchover clock oscillating unit 161 is thus supplied to the transmission PLL unit 150, so that the client-side clock is generated base on this supplied clock to transmit the AIS signals generated by the electrical signal processing unit 130 to the client-side via the optical transceiver unit 110.
Related-art transponders have the configurations and operations as described above. The problem is that frequency jump may occur in the PLL immediately after the switching of clocks during the downstream-side processing performed upon optical input interruption on the network side. This results in the failure to obtain a stable clock, thereby failing to transmit the AIS signals.
In the following, a mechanism by which frequency jump occurs will be described.
In FIG. 3 and FIG. 4, the clock switchover control unit 172 receives an optical input interruption detection signal upon the detection of optical input interruption by the optical input interruption detecting unit 121, and supplies a clock switchover control signal to the selector 173. The selector 173 selects the clock from the switchover clock oscillating unit 161 to provide the clock from the switchover clock oscillating unit 161 (after proper frequency division) to the transmission PLL unit 150.
In so doing, the flip-flop 152 and the EX-NOR gate 153 constituting the phase comparator of the transmission PLL unit 150 compares phases between the clock supplied from the voltage controlled oscillator 155 via the electrical signal processing unit 130 (i.e., a clock having its frequency properly divided after the voltage controlled oscillator 155) and the clock supplied from the switchover clock oscillating unit 161 selected by the selector 173 (i.e., a clock having its frequency properly divided after the switchover clock oscillating unit 161). Since these two clocks are asynchronous with each other even if their frequencies are the same, a phase jump of 180 degrees may occur at the maximum. The results of the phase comparison appear as a change in the output duty (i.e., the width of a high pulse in the output square wave). The above-noted phase jump causes an abrupt change in this output duty. As a result, a direct-current voltage obtained by smoothing the square wave by the low-pass filter 154 ends up having a large displacement from the stable-state level. The frequency of the voltage controlled oscillator 155 controlled by such a voltage thus exhibits a sudden change, which constitutes a frequency jump.
FIGS. 5A and 5B are drawings showing examples of operations of the transmission PLL unit 150 observed at the time of clock switching with respect to the downstream direction. FIG. 5A shows waveforms in the stable state, and FIG. 5B shows waveforms immediately after clock switching. In FIG. 5A, the clock of the voltage controlled oscillator 155 becomes the H level at the midpoint of the H-level period of the before-switchover clock (i.e., the clock supplied from the electrical signal processing unit 130), so that the output duty is set to 50% as a result of phase comparison. It follows that a direct-current voltage obtained through smoothing by the low-pass filter 154 is set to a level (1.65 V) that is about a half of the power supply voltage (3.3 V). In FIG. 5B, on the other hand, the after switchover clock (i.e., the clock supplied from the switchover clock oscillating unit 161) has a phase displacement of 180 degrees (in the worst case scenario), so that the output duty is set to 100% as a result of phase comparison. It follows that a direct-current voltage obtained through smoothing by the low-pass filter 154 is set to the same level as the power supply voltage (3.3 V).
A deviation of the center frequency of the clock required to transmit the AIS signals must be set within 20 ppm according to the standard. It naturally follows that the switchover clock oscillating unit 161 needs to have precision satisfying the 20-ppm requirement. In addition, the frequency precision becomes +165 ppm when the modulation sensitivity of the voltage controlled oscillator 155 is 100 ppm/V in the worst case scenario shown in FIG. 5B. It is thus almost impossible to satisfy the requirement. As time passes, the frequency jump disappears, and the deviation gradually becomes stable, so that the 20-ppm requirement will be met. Immediately after the switching, however, the clock cannot be used.
It may be possible to increase the delay of the time constant of the PLL response for the purpose of reducing a sudden change. However, such a sudden change cannot be completely avoided.
With respect to the upstream side that is opposite to the signal direction that has been described above, the frequency of the switchover clock oscillating unit 161 is set to match the bit rate on the client side as described above, so that the frequency dividing unit 164 is used to divide frequency after the switching of clocks by the selector 163. Because of this, a phase shift occurring immediately after clock switching has a reduced effect in commensurate with the ratio of the frequency division. Accordingly, frequency jump is not in existent immediately after clock switchover. FIG. 6 is a drawing showing an example of operation of the transmission PLL unit 140 observed at the time of clock switching with respect to the upstream direction. The frequency division ratio is assumed to be 1/10 for the sake of simplicity. There is an illustrated phase displacement (which is equal to 180 degrees corresponding to the worst case scenario) between a clock CLK#1 before frequency division (i.e., the clock supplied from the electrical signal processing unit 130) and a clock CLK#2 before frequency division (i.e., the clock supplied from the switchover clock oscillating unit 161). Such a phase displacement becomes minute when compared to one clock cycle after frequency division, thereby exerting only a negligible effect.
From the 10-Gbps optical transmission, a further speed increase is required to cope with recent traffic increases in communication apparatuses. A standard has already been set forth for 40-Gbps transmission speed apparatuses for use as the next-generation communication apparatuses, and efforts have been being made on the development of such apparatuses. The bit-rate increase due to the FEC process is defined to be different ratios between the 10-Gbps speed configuration and the 40-Gbps speed configuration according to the standard (ITU-T G.709). The bit rate on the client side and the bit rate on the network side are as follows.
Client SideNetwork SideClient:Network10 Gbps Bit Rate9.953280 Gbps10.709225 Gbps237:25540 Gbps Bit Rate39.81320 Gbps43.018500 Gbps236:255
In the case of 10 Gbps, the ratio of bit rates between the client side and the network side is 237:255. The greatest common divisor in this case is “3”. Frequency can thus be divided by “3” after clock switchover on the downstream side so as to slightly reduce an effect of phase shift based on the same principle as in the case of the upstream side described above. However, frequency division by 3 would not bring about sufficient improvement.
In the case of 40 Gbps that is expected to be widely used in the future, the ratio of bit rates between the client side and the network side is 236:255. There is no greatest common divisor in this case. The same principle as in the case of the upstream side previously described thus cannot be utilized. Namely, the output of the reference oscillator needs to be frequency-divided to perform frequency alignment before clock switchover, so that it is not possible to reduce an effect of phase shift by switching high-speed clocks first and then performing frequency division.
It should be noted that the provision of a new reference oscillator matching the frequency of the network side can remove an effect of phase shift on the downstream side. As previously described, however, the frequency on the network side corresponds to a special bit rate that is different from a generally used bit rate such as that of SDH. Further, the 20-ppm precision is needed to comply with the standard regarding frequency stability required for AIS transmission. New product development is thus necessary, which results in a cost increase due to the use of an expensive component. Such configuration is thus not a practically viable choice.
Patent Document 1 discloses technology for use in a clock switching control circuit of an ISDM connection apparatus. This technology prevents disturbance in the output clock at the time of switching input clocks into the PLL for generating multiple clocks. Patent Document 2 discloses technology that prevents an instantaneous interruption in an output clock signal and also reduces a phase shift at the time of switching operation.
These technologies do not take into account the special circumstances regarding transponders or the like as previously described, and cannot overcome the above-identified problems.
It may thus be desirable to provide an optical transmission apparatus that can stabilize a clock at the time of clock switchover performed upon optical input interruption.    [Patent Document 1] Japanese Patent Application Publication No. 2000-278261    [Patent Document 2] Japanese Patent Application Publication No. 8-8888